The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Apr. 28, 2023
Applicant:

Siliconch Systems Pvt Ltd, Karnataka, IN;

Inventors:

Rakesh Kumar Polasa, Karnataka, IN;

Alagesan Mani, Tamil Nadu, IN;

Assignee:

SILICONCH SYSTEMS PVT LTD, Karnataka, IN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318314 (2013.01); G01R 31/318536 (2013.01); G01R 31/318555 (2013.01);
Abstract

The present disclosure relates to an apparatus () for joint test action group (JTAG) and scan emulation, the apparatus includes a controller circuitry () that is interfaced to a target integrated circuit (IC) () for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices (--) operating in master mode and slave mode. The controller circuitry () operates the one or more SPI devices (--) to switch between a first mode and a second mode dynamically to emulate JTAG and scan test functionality. The controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.


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