The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Jan. 13, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Donghoon Kwon, Hwaseong-si, KR;

Chungki Min, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device includes a peripheral circuit structure including a lower substrate, a plurality of circuits formed on the lower substrate, and a plurality of wiring layers connected to the plurality of circuits, an upper substrate covering the peripheral circuit structure and including a through opening, a memory stack structure including a plurality of gate lines, a memory cell contact passing through at least one of the plurality of gate lines to contact one gate line from among the plurality of gate lines, the memory cell contact extending to the peripheral circuit structure through the through opening and being configured to be electrically connected to a first wiring layer from among the plurality of wiring layers, and a plurality of dummy channel structures passing through at least one of the plurality of gate lines to extend to the peripheral circuit structure through the through opening.


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