The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Aug. 01, 2023
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Julian Shaw Kelly, Santa Barbara, CA (US);

Evan Jeffrey, Santa Barbara, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/40 (2022.01); B82Y 10/00 (2011.01); G06N 10/00 (2022.01); H01L 23/00 (2006.01); H01L 25/04 (2023.01); H01L 25/065 (2023.01); H01L 25/07 (2006.01); H01L 25/075 (2006.01); H10N 69/00 (2023.01);
U.S. Cl.
CPC ...
G06N 10/40 (2022.01); G06N 10/00 (2019.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); B82Y 10/00 (2013.01); H01L 25/043 (2013.01); H01L 25/0657 (2013.01); H01L 25/074 (2013.01); H01L 25/0756 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13164 (2013.01); H01L 2224/13179 (2013.01); H01L 2224/13183 (2013.01); H01L 2224/13644 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06531 (2013.01); H01L 2225/06537 (2013.01); H10N 69/00 (2023.02);
Abstract

A device includes: a first chip including a plurality of qubits arranged in an array on a first side of the first chip, in which the array includes a plurality of qubit rows and a plurality of qubit columns, in which the plurality of qubits includes a first qubit row including two or more qubits and a second qubit row including two or more qubits, and in which the second qubit row is directly adjacent to the first qubit row; a second chip bonded to the first chip, in which the second chip has a first side that faces the first side of the first chip; a plurality of qubit control elements; a plurality of qubit readout resonators; and a plurality of qubit readout transmission lines.


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