The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Jul. 25, 2022
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Takatoshi Kameshima, Kanagawa, JP;

Hideto Hashiguchi, Kanagawa, JP;

Ikue Mitsuhashi, Kanagawa, JP;

Hiroshi Horikoshi, Tokyo, JP;

Reijiroh Shohji, Tokyo, JP;

Minoru Ishida, Tokyo, JP;

Tadashi Iijima, Kanagawa, JP;

Masaki Haneda, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/64 (2006.01); H01L 21/822 (2006.01); H01L 25/065 (2023.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 23/642 (2013.01); H01L 27/14634 (2013.01); H01L 21/8221 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01);
Abstract

A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.


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