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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12080611 B1

PDFFull Text
Date of Patent:
Sep. 03, 2024

Filed:

May. 17, 2021

Display device

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Moo Soon Ko, Seoul, KR;

Jeong-Soo Lee, Hwaseong-si, KR;

Jung Hwa Kim, Gunpo-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:

F. CHAU & ASSOCIATES, LLC

Primary Examiner:

Vincent Wall

Int. Cl.
CPC ...
H01L 21/66 (2006.01); G09G 3/00 (2006.01); G09G 3/3233 (2016.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H10K 59/12 (2023.01); H10K 59/88 (2023.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G09G 3/006 (2013.01); G09G 3/3233 (2013.01); H01L 27/1237 (2013.01); H01L 27/1248 (2013.01); H01L 27/1255 (2013.01); H01L 29/786 (2013.01); G09G 2300/0413 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0232 (2013.01); H10K 59/12 (2023.02); H10K 59/1201 (2023.02); H10K 59/88 (2023.02);
Abstract

A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.

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