Memory device including a plurality of stacked memory cells

Abstract

A memory device may include a bank layer and a control circuit layer. The bank layer may be arranged on a semiconductor substrate. The bank layer may include a plurality of mats. Each of the mats may include a plurality of stacked decks. Each of the decks may include a plurality of memory cells. The control circuit layer may be arranged between the semiconductor substrate and the bank layer. The control circuit layer may include a plurality of control circuit regions corresponding to the mats, respectively. The stacked decks may include a plurality of stacked word lines and a plurality of stacked bit lines intersected with the stacked word lines. A word line decoder, for controlling the word lines, and a bit line decoder, for controlling the bit lines, may be alternately and repeatedly arranged in the control circuit layer.