The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Jan. 31, 2022
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventor:

Kedar Rajpathak, Bengaluru, IN;

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G01R 31/31727 (2013.01);
Abstract

Methods and structures are described for detecting clock anomalies, including anomalies in which the clock oscillates at a faster than expected rate or exhibits a shorter than expected clock phase instance. Example methods include starting a timer responsive to the start of a clock phase, wherein the timer duration is shorter than an expected duration of the clock phase. If the clock phase ends before the timer expires, a fast clock detection signal is asserted. Example structures include fast clock detection logic coupled to a clock signal. The logic includes a timer, circuitry to start the timer responsive to the clock signal entering a monitored phase, and error detection circuitry to assert a fast clock detection output if the monitored phase ends before the timer expires. In some embodiments, the timer duration may be based on a measured duration of a previous clock phase.


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