The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Jun. 06, 2023
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Giorgio Allegato, Monza, IT;

Sonia Costantini, Missaglia, IT;

Federico Vercesi, Milan, IT;

Roberto Carminati, Piancogno, IT;

Assignee:

STMicroelectron S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 26/10 (2006.01); B81C 1/00 (2006.01); G02B 26/08 (2006.01);
U.S. Cl.
CPC ...
G02B 26/105 (2013.01); B81C 1/00317 (2013.01); B81C 1/00523 (2013.01); G02B 26/0833 (2013.01); B81B 2201/042 (2013.01); B81C 2203/0109 (2013.01); B81C 2203/019 (2013.01);
Abstract

A method of making a MEMS device including forming a mirror stack on a handle layer, applying a first bonding layer to the mirror stack, and disposing a substrate on the first bonding layer. The handle layer is removed and a second bonding layer is applied. A cap layer is disposed on the second bonding layer. The mirror stack is formed by disposing a silicon layer on the handle layer, disposing a first insulating layer on the silicon layer, etching portions of the first insulating layer, and depositing a first conductive layer on the first insulating layer. The formation also includes depositing a second insulating layer on the first conductive layer, a portion of the second insulating layer to expose a portion of the first conductive layer exposed, and forming a conductive pad on the exposed portion of the first conductive layer.


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