The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Oct. 12, 2020
Applicants:

Sony Group Corporation, Tokyo, JP;

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Tomoko Katsuhara, Tokyo, JP;

Hiizu Ohtorii, Kanagawa, JP;

Kei Tsukamoto, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01L 1/24 (2006.01); H05K 1/02 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
G01L 1/247 (2013.01); G01L 1/241 (2013.01); H05K 1/0274 (2013.01); H05K 1/141 (2013.01); H05K 1/181 (2013.01); H05K 2201/0367 (2013.01); H05K 2201/10151 (2013.01);
Abstract

An optical sensor according to an embodiment of the present disclosure includes a light emitting substrate and a circuit board. The light emitting substrate includes a light emitting device. The circuit board is provided at a position opposing the light emitting device. The circuit board includes a light transmitting section and one or multiple light receiving devices. The light transmitting section transmits light of the light emitting device. The one or multiple light receiving devices receive light reflected by a reflective layer of the light of the light emitting device exiting through the light transmitting section. For example, the one or multiple light receiving devices are formed on a first major surface of the circuit board. For example, the light emitting substrate is disposed at a position opposing a second major surface, of the circuit board, on an opposite side to the first major surface, and is stacked on the circuit board with a first bump interposed therebetween.


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