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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12075673 B1

PDFFull Text
Date of Patent:
Aug. 27, 2024

Filed:

Jul. 06, 2023

Display panel comprising a data line including sub-data lines and display device having the same

Applicant:

Wuhan Tianma Micro-electronics Co., Ltd., Wuhan, CN;

Inventors:

Xingxing Yang, Wuhan, CN;

Yangzhao Ma, Wuhan, CN;

Zhiqiang Xia, Wuhan, CN;

Assignee:

Wuhan Tianma Micro-Electronics Co., Ltd., Wuhan, CN;

Attorney:

Anova Law Group, PLLC

Primary Examiner:

Phuc T Dang

Int. Cl.
CPC ...
H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 59/88 (2023.01); H01L 27/12 (2006.01); H10K 59/35 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/88 (2023.02); H01L 27/1214 (2013.01); H10K 59/35 (2023.02);
Abstract

A display panel includes a first display region, a second display region, a third display region, a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of third pixel circuits, a plurality of first data lines, and a plurality of second data lines. The second display region at least partially surrounds the first display region, the third display region at least partially surrounds the second display region and the first display region, and a light transmittance of the first display region is greater than a light transmittance of the third display region. The plurality of first pixel circuits and the plurality of second pixel circuits are in the second display region, and the plurality of third pixel circuits is in the third display region. The plurality of first data lines are connected to the plurality of first pixel circuits and the plurality of third pixel circuits.

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