The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2024
Filed:
Oct. 18, 2022
Image signal and phase detection autofocus signal extraction and storage in an arithmetic logic unit
Applicant:
Omnivision Technologies, Inc., Santa Clara, CA (US);
Inventor:
Rui Wang, San Jose, CA (US);
Assignee:
OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/772 (2023.01); G06F 7/501 (2006.01); G06F 7/57 (2006.01);
U.S. Cl.
CPC ...
H04N 25/772 (2023.01); G06F 7/501 (2013.01); G06F 7/57 (2013.01);
Abstract
An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.