The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Jun. 07, 2023
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Sung-Ik Park, Daejeon, KR;

Heung-Mook Kim, Daejeon, KR;

Sun-Hyoung Kwon, Daejeon, KR;

Nam-Ho Hur, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/03 (2006.01); H03M 13/27 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1157 (2013.01); H03M 13/1165 (2013.01); H03M 13/616 (2013.01); H03M 13/036 (2013.01); H03M 13/1185 (2013.01); H03M 13/2792 (2013.01); H03M 13/6552 (2013.01); H04L 1/0041 (2013.01); H04L 1/0043 (2013.01); H04L 1/0057 (2013.01); H04L 1/0058 (2013.01); H04L 1/0071 (2013.01);
Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).


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