The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Dec. 05, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyung-Joong Kim, Seoul, KR;

Se-ho Myung, Yongin-si, KR;

Hong-sil Jeong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/25 (2006.01); H04L 1/00 (2006.01); G06F 11/10 (2006.01); H03M 13/15 (2006.01); H03M 13/29 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1157 (2013.01); H03M 13/1165 (2013.01); H03M 13/255 (2013.01); H03M 13/618 (2013.01); H04L 1/0041 (2013.01); G06F 11/1004 (2013.01); H03M 13/1148 (2013.01); H03M 13/1191 (2013.01); H03M 13/152 (2013.01); H03M 13/253 (2013.01); H03M 13/2906 (2013.01); H03M 13/611 (2013.01); H04L 1/0057 (2013.01); H04L 1/0063 (2013.01); H04L 1/0069 (2013.01);
Abstract

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.


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