The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Nov. 08, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Gyu Tae Park, Icheon-si, KR;

Young Suk Seo, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01);
Abstract

A duty correction circuit comprises a first delay circuit, a second delay circuit, a bang-bang driver, a duty detection circuit, and a delay control circuit. The first delay circuit delays an input clock signal to generate a first delayed clock signal. The second delay circuit delays the input clock signal based on a delay control signal to generate a second delayed clock signal. The bang-bang driver generates first and second driving clock signals from the first and second delayed clock signals based on a locking signal and a duty detection signal. The duty detection circuit may detect duty cycles of the first and second driving clock signals and generate the duty detection signal. The delay control circuit may generate the delay control signal and the locking signal based on the duty detection signal.


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