The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Dec. 02, 2019
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Timothy Edward Boles, Tyngsboro, MA (US);

James Joseph Brogle, Merrimac, MA (US);

Joseph Gerard Bukowski, Derry, NH (US);

Margaret Mary Barter, Lowell, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/868 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/868 (2013.01); H01L 21/26513 (2013.01); H01L 29/0688 (2013.01); H01L 29/6609 (2013.01);
Abstract

A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes an N-type silicon substrate, an intrinsic layer formed on the N-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first P-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second P-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional P-type regions can be formed to other depths.


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