The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Dec. 08, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Moorym Choi, Yongin-si, KR;

Yoonjo Hwang, Gimpo-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/535 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 23/535 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a stack structure having alternating interlayer dielectric layers and gate electrodes, a first insulating layer covering the stack structure, and a second substrate on the stack structure and the first insulating layer, the stack structure being between a bottom surface of the second substrate and the peripheral circuit structure, a second insulating layer on the cell array structure, a first penetration contact penetrating the first insulating layer, the second substrate, and the second insulating layer, and a second penetration contact penetrating the first insulating layer and the second insulating layer, the second penetration contact being spaced apart from the second substrate, and the first and second penetration contacts having widths decreasing with increasing distance from the first substrate.


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