The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Jul. 28, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eun-Ji Kim, Suwon-si, KR;

Jung-June Park, Seoul, KR;

Jeong-Don Ihm, Seongnam-si, KR;

Byung-Hoon Jeong, Hwaseong-si, KR;

Young-Don Choi, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 16/06 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 29/025 (2013.01); G11C 5/063 (2013.01); G11C 7/1048 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/06 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01);
Abstract

A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.


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