Semiconductor memory device with write disturb reduction

Abstract

A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical '1' step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.