The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Mar. 28, 2023
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Dario Livornesi, Milan, IT;

Alessio Emanuele Vergani, Milan, IT;

Paolo Pulici, Legnano, IT;

Francesco Piscitelli, Milan, IT;

Enrico Mammei, Vittuone, IT;

Mojtaba Mohammadi Abdevand, Pavia, IT;

Piero Malcovati, Pavia, IT;

Edoardo Bonizzoni, Pavia, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/60 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
G11B 5/6029 (2013.01); G11B 5/607 (2013.01); H03F 1/0261 (2013.01);
Abstract

According to an embodiment, a circuit includes a biasing and a low-frequency recovery circuit. The biasing circuit includes a voltage digital to analog converter (V-DAC), a differential difference amplifier coupled to the V-DAC, a common-mode feedback (CMFB) amplifier coupled to the differential difference amplifier, and a first pair of transistors arranged as a high-impedance structure and coupled to the differential difference amplifier and the CMFB amplifier. The low-frequency recovery circuit includes a current digital to analog converter (C-DAC), a second pair of transistors arranged as a high-impedance structure and coupled to the first pair of transistors, a pair of resistors having a resistance value equal to half a resistance of the resistive sensor, the pair of resistors arranged between the second pair of transistors and coupled to the C-DAC, and a gain circuit coupled to shared nodes between the second pair of transistors and the pair of resistors.


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