The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Mar. 02, 2023
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Anurag Chaudhary, San Jose, CA (US);

Scott Matthew Pitkethly, Tampa, FL (US);

Peter Lindsay Gentle, San Jose, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/161 (2013.01); G06F 13/4027 (2013.01); G06F 2213/0038 (2013.01);
Abstract

Various embodiments include a network for transmitting data words from a source node to a destination node. The source node optionally inverts the logic levels of each data word so that the number of logic '1' bits in each data word is less than or equal to half of the data bits. The destination node recovers the original data words by passing the data words not inverted by the source node and inverting the data words that were inverted by the source node. As the packet is transmitted through the network, each node encodes and/or decodes the data words by generating an output transition for each logic ‘1’ bit of the input data word. Because no more than half the bits of the input data word are logic ‘1’ bits, the node generates output transitions for no more than one half of the data bits.


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