The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Mar. 10, 2021
Applicant:

Keysight Technologies, Inc., Santa Rosa, CA (US);

Inventor:

Andrew Michael Owen, Lake Villa, IL (US);

Assignee:

KEYSIGHT TECHNOLOGIES, INC., Santa Rosa, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 23/16 (2006.01); G01R 23/165 (2006.01); H04B 1/10 (2006.01); G06F 3/02 (2006.01);
U.S. Cl.
CPC ...
G01R 23/165 (2013.01); H04B 1/1027 (2013.01); G06F 3/02 (2013.01);
Abstract

Methods, devices, and systems for coherent time-gated residual spur characterization and correction in signal analyzers. In some cases, the method includes: displaying a signal on the display of the signal analyzer that is present without an input signal being provided to an input of the signal analyzer; establishing a predetermined amplitude threshold above which energy spikes in the signal being displayed on the display of the signal analyzer are considered spurious; automatically identifying one or more spurious energy spikes in the signal being displayed on the display of the signal analyzer based on the predetermined amplitude threshold; and automatically reducing or removing the one or more spurious energy spikes from the signal being displayed on the display of the signal analyzer. The method can be performed using one or more processors, application specific integrated circuits (ASICs), field-programmable gate array (FPGA), or other circuitry on any suitable signal analyzer.


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