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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12069897 B1

PDFFull Text
Date of Patent:
Aug. 20, 2024

Filed:

Sep. 30, 2022

Organic light-emitting diode (oled) display having a semiconductor layer including a third portion extending in a third direction joining a first and second portions that extending in different directions

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Moo Soon Ko, Seoul, KR;

Jung Hwa Kim, Gunpo-si, KR;

Min Woo Woo, Bucheon-si, KR;

Wang Woo Lee, Osan-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:

F. Chau & Associates, LLC

Primary Examiner:

Anh D Mai

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 59/35 (2023.01); H10K 59/38 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H01L 27/1222 (2013.01); H01L 27/124 (2013.01); H10K 59/121 (2023.02); H10K 59/131 (2023.02); H10K 59/352 (2023.02); H10K 59/353 (2023.02); H10K 59/38 (2023.02);
Abstract

An organic light-emitting diode display is disclosed. In one aspect, a semiconductor layer is on a substrate, and the semiconductor layer is non-linear. A gate metal line is on the semiconductor layer, and an insulating layer covering the semiconductor layer and the gate metal line and having a plurality of contact holes connected to the semiconductor layer. A data metal line is on the insulating layer and electrically connected to the semiconductor layer via a selected one of the contact holes. An OLED is electrically connected to the gate metal line and the data metal line, and the semiconductor layer includes a narrow semiconductor layer having a first width and an expansion semiconductor layer formed adjacent to the selected contact hole and having a second width greater than the first width.

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