The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Dec. 06, 2021
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Jieun Lee, Yongin-si, KR;

Minchae Kwak, Yongin-si, KR;

Byungsun Kim, Yongin-si, KR;

Ilgoo Youn, Yongin-si, KR;

Seunghan Jo, Yongin-si, KR;

Junyoung Jo, Yongin-si, KR;

Minhee Choi, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/12 (2006.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H01L 27/1225 (2013.01);
Abstract

Provided is a display apparatus including: a substrate in which a display element is arranged; a first thin film transistor arranged in the display area and including a first semiconductor layer including silicon and a first control electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first control electrode; a second thin film transistor arranged on the first interlayer insulating layer and including a second semiconductor layer including an oxide semiconductor and a second control electrode insulated from the second semiconductor layer; a second interlayer insulating layer covering the second control electrode; a node connection line arranged on the second interlayer insulating layer and connected to the first control electrode via a first contact hole; a first planarization layer covering the node connection line; and a shielding electrode arranged on the first planarization layer to overlap the node connection line.


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