The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Mar. 23, 2020
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Qi Wang, Beijing, CN;

Yiyang Jiang, Beijing, CN;

Qianhui Li, Beijing, CN;

Zongliang Huo, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/15 (2006.01); H03M 13/39 (2006.01); G06F 11/00 (2006.01); G11C 29/52 (2006.01); H03M 13/25 (2006.01); H03M 13/29 (2006.01); H03M 13/37 (2006.01); H03M 13/45 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1111 (2013.01); H03M 13/154 (2013.01); H03M 13/3927 (2013.01); G06F 11/00 (2013.01); G11C 29/52 (2013.01); H03M 13/1108 (2013.01); H03M 13/255 (2013.01); H03M 13/2948 (2013.01); H03M 13/3746 (2013.01); H03M 13/45 (2013.01);
Abstract

The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.


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