The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Jan. 21, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyongsik Yeom, Suwon-si, KR;

Youngcheon Jeong, Hwaseong-si, KR;

Yongkyu Lee, Gwacheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 29/42328 (2013.01); H01L 29/42336 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H10B 41/35 (2023.02); H10B 41/41 (2023.02);
Abstract

An integrated circuit includes; a source region arranged in an upper portion of a substrate, a pair of split gate structures respectively on opposing sides of the source region, wherein each of the pair of split gate structures includes a floating gate electrode layer and a control gate electrode layer disposed on the floating gate electrode layer, an erase gate structure between the pair of split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures respectively on outer sidewalls of the pair of split gate structures, and a pair of gate spacers, wherein each of the gate spacers is disposed between one of the pair of split gate structures and one of the pair of selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, is further disposed on an outer side wall of the one of the pair of split gate structures, and a lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.


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