The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Feb. 28, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young-Hun Kim, Seoul, KR;

Jae-Seok Yang, Hwaseong-si, KR;

Hae-Wang Lee, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 2027/11829 (2013.01); H01L 2027/11861 (2013.01); H01L 2027/11864 (2013.01); H01L 2027/11881 (2013.01);
Abstract

A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.


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