The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Jun. 10, 2021
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Giovanni Graziosi, Vimercate, IT;

Michele Derai, Milan, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 24/82 (2013.01); H01L 23/295 (2013.01); H01L 23/3135 (2013.01); H01L 23/49589 (2013.01); H01L 23/645 (2013.01); H01L 23/647 (2013.01); H01L 24/48 (2013.01); H01L 24/96 (2013.01); H01L 23/49513 (2013.01); H01L 23/49582 (2013.01); H01L 24/92 (2013.01); H01L 2224/24105 (2013.01); H01L 2224/24175 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48265 (2013.01); H01L 2224/82101 (2013.01); H01L 2224/82106 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/186 (2013.01);
Abstract

Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.


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