The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Oct. 01, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byung Hyun Lee, Suwon-si, KR;

Sung-Ok Lee, Hwaseong-si, KR;

Sang Do Park, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 23/481 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01);
Abstract

A semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device are provided. The semiconductor device includes a standard cell region. The semiconductor device includes a substrate including a first surface and a second surface, which are opposite to each other, a first power wiring, which extends in a first direction on the first surface of the substrate, and is configured to provide a first power voltage to the standard cell region, a second power wiring, which extends in the first direction on the first surface of the substrate, is arranged alternately with the first power wiring in a second direction intersecting the first direction, and is configured to provide a second power voltage different from the first power voltage to the standard cell region, a first back routing wiring on the second surface of the substrate, and a plurality of first tab cell regions arranged along the second direction, wherein each of the first tab cell regions includes a first through via, which penetrates the substrate and connects the first power wiring and the first back routing wiring.


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