Cache memory with decoupled control paths

Abstract

An example cache memory includes a schedule module, control modules, a datapath, and an output module. The cache memory receives requests to read and/or write cache lines. The schedule module maintains a queue of the requests. The schedule module may assign the requests to the control modules based on the queue. A control module, which receives a request, controls the datapath to execute the request, i.e., to read or write the cache line. The control module can control the execution by the datapath from start to end. Multiple control modules may control parallel executions by the datapath. The output module outputs, e.g., to a processor, responses of the cache memory to the requests after the executions. A response may include a cache line. The cache memory may include a buffer that temporarily stores cache lines before the output to avoid deadlock in the datapath during the parallel executions of requests.