The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Mar. 03, 2023
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventors:

Xiaosong Zhang, Boise, ID (US);

Yi Hu, Boise, ID (US);

Tom J. John, Boise, ID (US);

Wei Yeeng Ng, Boise, ID (US);

Chandra Tiwari, Boise, ID (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/311 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/31111 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02);
Abstract

In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.


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