The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Aug. 13, 2019
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Manabu Tomita, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 23/5286 (2013.01); H01L 27/092 (2013.01); H01L 29/0676 (2013.01); H01L 29/42392 (2013.01); H01L 29/775 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H10B 10/125 (2023.02);
Abstract

A memory cell includes a flip-flop circuit that includes a first CMOS inverter circuit including a 1Ath transistor TRand a 1Bth transistor TRand a second inverter circuit including a 2Ath transistor TRand a 2Bth transistor TRand two transfer transistors TRand TR. The 1Ath transistor TRand the 2Ath transistor TRare connected to a common first power supply line, and the 1Bth transistor TRand the 2Bth transistor TRare connected to a common second power supply line.


Find Patent Forward Citations

Tomita, Manabu. (2024). Memory cell and cmos inverter circuit (U.S. Patent No. 12063765). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12063765

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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