The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Mar. 24, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yongsun Lee, Suwon-si, KR;

Jaewoo Park, Suwon-si, KR;

Myoungbo Park, Suwon-si, KR;

Jinook Jung, Suwon-si, KR;

Junghwan Choi, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/093 (2006.01); H03L 7/081 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); H03L 7/0818 (2013.01); H03L 7/0991 (2013.01);
Abstract

A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.


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