The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2024
Filed:
Aug. 16, 2022
Applicant:
Socionext Inc., Kanagawa, JP;
Inventor:
Junji Iwahori, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/412 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 27/118 (2006.01); H01L 29/06 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); G11C 11/412 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/11807 (2013.01); H10B 10/12 (2023.02); H01L 2027/11881 (2013.01);
Abstract
A layout structure of a capacitive cell using forksheet FETs is provided. In transistors Pand N, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.