The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Dec. 27, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Joonsung Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 23/3121 (2013.01); H01L 23/34 (2013.01); H01L 23/5226 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 23/3171 (2013.01); H01L 2224/08235 (2013.01);
Abstract

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.


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