The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Jun. 15, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Zhao Lu, Ebina, JP;

Yuji Nagai, Sagamihara, JP;

Akio Sugahara, Yokohama, JP;

Takehisa Kurosawa, Yokohama, JP;

Masaru Koyanagi, Ota, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/08 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01);
Abstract

A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.


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