Method and system for registering circuit design layout and scanning electron microscope image, circuit design layout and imaging error calculation method thereof, and electronic device

Abstract

The present invention provides a method for registering a circuit design layout and a scanning electron microscope image. The method comprises: step S, providing a circuit design layout and a scanning electron microscope image; step S: processing the circuit design layout to acquire a binary design layout image, and processing the scanning electron microscope image to acquire a binary scanning electron microscope image; step S: performing Gaussian filtering on the binary design layout image and the binary scanning electron microscope image to maximize a gray value at a central axis of regions corresponding to a design pattern and a scanned pattern; and Step S: performing registration according to the central axis of the design pattern and the scanned pattern. The present invention also provides a system for registering a circuit design layout and a scanning electron microscope image, a circuit design layout and an imaging error calculation method thereof, and an electronic device. The method and system for registering a circuit design layout and a scanning electron microscope image, the circuit design layout and the imaging error calculation method thereof, and the electronic device feature accurate registration and accurate error calculation.