The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Apr. 14, 2020
Applicant:

Celerint, Llc, New York, NY (US);

Inventors:

Howard H. Roberts, Jr., San Antonio, TX (US);

LeRoy Growt, Pflugerville, TX (US);

Assignee:

CELERINT, LLC, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31703 (2013.01); G01R 31/31725 (2013.01); H04L 7/0091 (2013.01);
Abstract

A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.


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