The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Sep. 24, 2021
Applicant:

Icometrue Company Ltd., Zhubei, TW;

Inventors:

Jin-Yuan Lee, Hsinchu, TW;

Mou-Shiung Lin, Hsinchu, TW;

Assignee:

iCometrue Company Ltd., Hsin-Chu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/1776 (2020.01); G11C 11/16 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); G11C 13/00 (2006.01); G11C 14/00 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01); H03K 19/0948 (2006.01); H03K 19/173 (2006.01); H03K 19/17728 (2020.01); H03K 19/20 (2006.01); H10B 10/00 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); G11C 11/1673 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); G11C 13/0007 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01); G11C 14/0081 (2013.01); G11C 14/009 (2013.01); H01L 23/49811 (2013.01); H01L 23/5386 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H03K 19/0948 (2013.01); H03K 19/1737 (2013.01); H03K 19/17728 (2013.01); H03K 19/20 (2013.01); H10B 10/00 (2023.02); H10B 10/15 (2023.02); H10B 61/00 (2023.02); H10B 61/10 (2023.02); H10B 63/00 (2023.02); H10B 63/20 (2023.02); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); G11C 2213/15 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/83104 (2013.01); H01L 2224/92225 (2013.01); H01L 2224/97 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1443 (2013.01); H03K 19/21 (2013.01);
Abstract

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.


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