The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Jul. 10, 2020
Applicants:

Arizona Board of Regents on Behalf of Arizona State University, Scottsdale, AZ (US);

The Texas A&m University System, College Station, TX (US);

Inventors:

Sarma Vrudhula, Chandler, AZ (US);

Sunil Khatri, College Station, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01); H03K 19/00 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0027 (2013.01); G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/28 (2013.01); G11C 16/3404 (2013.01); G11C 29/32 (2013.01);
Abstract

Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.


Find Patent Forward Citations

Loading…