The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Aug. 09, 2021
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Hiroshi Horikoshi, Tokyo, JP;

Minoru Ishida, Tokyo, JP;

Reijiroh Shohji, Tokyo, JP;

Tadashi Iijima, Kanagawa, JP;

Takatoshi Kameshima, Kanagawa, JP;

Hideto Hashiguchi, Kanagawa, JP;

Ikue Mitsuhashi, Kanagawa, JP;

Masaki Haneda, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 27/14634 (2013.01); H01L 27/14683 (2013.01); H01L 23/481 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06135 (2013.01);
Abstract

Provided is a solid-state imaging device that includes a first substrate which includes a first semiconductor substrate and a first multi-layered wiring layer that are stacked, a second substrate which includes a second semiconductor substrate and a second multi-layered wiring layer that are stacked, and a third substrate which includes a third semiconductor substrate and a third multi-layered wiring layer that are stacked. The solid-state imaging device further includes a first coupling structure for electrically coupling a circuit of the first substrate and a circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or a predetermined wiring line in the third multi-layered wiring layer to each other.


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