The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

May. 12, 2021
Applicant:

Magnachip Semiconductor, Ltd., Cheongju-si, KR;

Inventors:

Kyong Jin Hwang, Cheongju-si, KR;

Hyun Kwang Jeong, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/28 (2006.01); H01L 27/06 (2006.01); H01L 29/423 (2006.01); H01L 29/43 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H03K 19/003 (2006.01); H03K 19/0185 (2006.01); H01L 29/06 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01); H01L 21/28052 (2013.01); H01L 27/0255 (2013.01); H01L 27/0288 (2013.01); H01L 27/0629 (2013.01); H01L 29/42368 (2013.01); H01L 29/435 (2013.01); H01L 29/4916 (2013.01); H01L 29/4933 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01); H03K 19/00361 (2013.01); H03K 19/018507 (2013.01); H01L 29/0692 (2013.01); H01L 29/861 (2013.01);
Abstract

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.


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