The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

May. 28, 2019
Applicant:

Epicmems (Xiamen) Co., Ltd., Fujian, CN;

Inventors:

Wei Wang, Fujian, CN;

Ping Li, Fujian, CN;

Yanhao Peng, Fujian, CN;

Nianchu Hu, Fujian, CN;

Bin Jia, Fujian, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/28 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3135 (2013.01); H01L 21/4814 (2013.01); H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/645 (2013.01); H01L 24/16 (2013.01); H01L 24/20 (2013.01); H01L 25/0655 (2013.01); H01L 23/564 (2013.01); H01L 24/81 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/81801 (2013.01);
Abstract

A chip encapsulation structure, including: a wafer provided with a groove; a first metal wire arranged on surfaces of the groove and the wafer; a metal solder ball arranged on the first metal wire or on a metal pad of the chip, and is configured to solder the metal pad of the chip to the first metal wire; a first plastic encapsulation film covering upper surfaces of the wafer, the chip and the first metal wire, and entering a gap between a periphery of a functional area of the chip and the first metal wire, so as to form a closed cavity among the wafer, the groove and the chip; an inductive structure arranged on an upper surface of the first plastic encapsulation film and/or a lower surface of the wafer, and connected to the chip through the first metal wire; and a pad arranged on the inductive structure.


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