The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Jul. 10, 2017
Applicant:

Ayar Labs, Inc., San Francisco, CA (US);

Inventors:

Chen Sun, Berkeley, CA (US);

Roy Edward Meade, Oakland, CA (US);

Mark Wade, Berkeley, CA (US);

Alexandra Wright, San Francisco, CA (US);

Vladimir Stojanovic, Berkeley, CA (US);

Assignee:

Ayar Labs, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/304 (2006.01); B05D 1/00 (2006.01); G02B 6/12 (2006.01); G02B 6/122 (2006.01); G02B 6/36 (2006.01); G03F 7/16 (2006.01); G03F 9/00 (2006.01); H01L 21/67 (2006.01); H01S 5/026 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6715 (2013.01); B05D 1/005 (2013.01); G02B 6/12004 (2013.01); G02B 6/1225 (2013.01); G02B 6/3692 (2013.01); G03F 7/162 (2013.01); G03F 9/708 (2013.01); G03F 9/7084 (2013.01); H01S 5/0265 (2013.01); G02B 2006/12061 (2013.01);
Abstract

A photoresist material is deposited, patterned, and developed on a backside of a wafer to expose specific regions on the backside of chips for etching. These specific regions are etched to form etched regions through the backside of the chips to a specified depth within the chips. The specified depth may correspond to an etch stop material. Etching of the backside of the wafer can also be done along the chip kerf regions to reduce stress during singulation/dicing of individual chips from the wafer. Etching of the backside of the chips can be done with the chips still part of the intact wafer. Or, the wafer having the pattered and developed photoresist on its backside can be singulated/diced before etching through the backside of the individual chips. The etched region(s) formed through the backside of a chip can be used for attachment of optical component(s) to the chip.


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