The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Sep. 21, 2022
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Francesco La Rosa, Rousset, FR;

Antonino Conte, Tremestieri Etneo, IT;

Francois Maugain, Trets, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01);
U.S. Cl.
CPC ...
G11C 16/3445 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 16/349 (2013.01); H10B 41/30 (2023.02); H10B 41/40 (2023.02);
Abstract

In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.


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