The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Sep. 30, 2020
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Jonathan Cohen, Hod Hasharon, IL;

Said Bshara, Tira, IL;

Leah Shalev, Zichron Yaakov, IL;

Erez Izenberg, Tel Aviv, IL;

Rotem Shaanan, Sal'it, IL;

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 9/30 (2018.01); G06F 13/28 (2006.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 9/30101 (2013.01); G06F 13/161 (2013.01); G06F 13/1642 (2013.01); G06F 13/28 (2013.01); G06F 15/17375 (2013.01); G06F 15/7807 (2013.01);
Abstract

Systems and methods are provided to reduce the latency in accessing an input/output (I/O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I/O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I/O bus.


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