The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2024

Filed:

Nov. 03, 2021
Applicant:

Ppip Llc, Chandler, AZ (US);

Inventors:

Michael Fong, Chandler, AZ (US);

Neric Hsin-wu Fong, Tempe, AZ (US);

Mohamad Ahmad Foustok, Parkland, FL (US);

Ryan Mark Speers, Silver Spring, MD (US);

Assignee:

PPIP, LLC, Chandler, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/08 (2006.01); H04L 9/14 (2006.01); H04L 9/40 (2022.01); H04M 1/72409 (2021.01);
U.S. Cl.
CPC ...
H04L 9/0894 (2013.01); H04L 9/0825 (2013.01); H04L 63/029 (2013.01); H04L 63/0876 (2013.01);
Abstract

In accordance with some embodiments, a secure modular apparatus providing a first platform for secure platform integration includes communication device(s) and a key store for storing encryption keys. The apparatus additionally includes a crypto engine operable to use the encryption keys for cryptographic operations. The apparatus also includes a controller and a housing arranged to at least partially support the communication device(s), the key store, the crypto engine, and the controller. The controller, via the communication device(s), exchanges encrypted messages prepared or processed by the crypto engine with a second platform provided by a personal communication device, where the second platform is distinct from the first platform and has a plurality of layers including at least one layer between a hardware layer and high level layers, and the encrypted messages control one or more of a hardware unit in the hardware layer and a component in the high level layers.


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