The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2024

Filed:

Feb. 01, 2021
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Masaki Nagata, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/42364 (2013.01); H01L 29/66734 (2013.01);
Abstract

There is provided a semiconductor device, including: a semiconductor chip including a main surface; a gate trench formed on the main surface; a first insulating film configured to cover an upper wall surface of the gate trench; a second insulating film configured to cover a lower wall surface of the gate trench; a field trench formed on the main surface so as to be spaced apart from the gate trench, and including a facing wall at a side of the gate trench and a non-facing wall at an opposite side of the facing wall; a third insulating film configured to cover an upper wall surface of the field trench at a side of the facing wall; and a fourth insulating film configured to cover a lower wall surface of the field trench at the side of the facing wall and the non-facing wall.


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