The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2024
Filed:
Mar. 06, 2023
Applicant:
Lodestar Licensing Group Llc, Evanston, IL (US);
Inventor:
Richard C. Murphy, Boise, ID (US);
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G06F 9/30 (2018.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 12/0864 (2016.01); G06F 12/0895 (2016.01); G11C 7/10 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G11C 11/4094 (2006.01); G11C 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0864 (2013.01); G06F 9/30036 (2013.01); G06F 12/0811 (2013.01); G06F 12/084 (2013.01); G06F 12/0895 (2013.01); G11C 7/1006 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G06F 2212/1012 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/283 (2013.01); G06F 2212/6032 (2013.04); G11C 11/4094 (2013.01); G11C 19/00 (2013.01);
Abstract
The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.