The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Apr. 24, 2020
Applicants:

Magna International Inc., Aurora, CA;

University of Windsor, Windsor, CA;

Inventors:

Animesh Kundu, Windsor, CA;

Aiswarya Balamurali, Windsor, CA;

Himavarsha Dhulipati, Windsor, CA;

Narayan Chandra Kar, Windsor, CA;

Lakshmi Varaha Iyer, Troy, MI (US);

Gerd Schlager, St. Valentin, AT;

Philip Korta, Troy, MI (US);

Wolfgang Baeck, St. Valentin, AT;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02P 27/08 (2006.01); B60L 15/00 (2006.01); H02M 1/00 (2006.01); H02M 1/084 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
H02M 7/53871 (2013.01); B60L 15/007 (2013.01); H02M 1/0058 (2021.05); H02M 1/084 (2013.01); H02P 27/08 (2013.01); B60L 2210/44 (2013.01);
Abstract

A motor drive system for an electrified vehicle includes a DC source, such as a battery, and an inverter, which includes one or more phase drivers, each configured to switch current from the DC source to generate AC power upon one or more output terminals using a hybrid of two or more different solid-state switches, each having a corresponding voltage rating. A nine-switch inverter includes three phase drivers, each including high, low, and middle solid-state switches, with Si-MOSFET high and low switches having a first voltage rating of half of the rated voltage of the system, and with Gallium Nitride (GaN) transistors rated to block a full rated voltage of the system used for the middle switches. A delay driver synchronizes timing between two different solid-state switches by energizing control terminals at different rates. The inverter can be operated using near-state pulse-width modulation (NSPWM) to reduce switching losses.


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