Semiconductor with faster conduction for rapid writing to memory

Abstract

A semiconductor with 3D flash memory storing cells includes a stack structure in each storing cell, a blocking layer, at least one floating gate layer, a tunnel dielectric layer, and a channel layer. The stack structure includes at least one control gate layer, at least one dielectric layer, and at least one erasing layer. The blocking layer is coplanar with the control gate layer. The floating layer is received in the blocking layer, and insulates the control gate layer by the blocking layers. The tunnel dielectric layer covers sides of the blocking layer and the floating gate layer. The channel layer is placed on a side of the tunnel electric layer. When the storing cell executes a data reading and writing process, a voltage is applied on the erasing layer to reduce a series resistance of the channel layer for rapid conduction by the semiconductor.